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TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
DRAM
FEATURES
* Industry-standard x16 pinouts, timing, functions and packages * High-performance CMOS silicon-gate process * Single +5V 10% power supply* * Low power, 3mW standby; 300mW active, typical * All device pins are TTL-compatible * 512-cycle refresh in 8ms (9 row- and 9 column addresses) * Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN * Extended Data-Out (EDO) PAGE MODE access cycle * BYTE WRITE and BYTE READ access cycles
256K x 16 DRAM
5V, EDO PAGE MODE
PIN ASSIGNMENT (Top View) 40-Pin SOJ (DA-6)
OPTIONS
* Timing 40ns access 50ns access 60ns access * Packages Plastic SOJ (400 mil)
MARKING
-4* -5* -6 DJ
* Part Number Example: MT4C16270DJ-4
*40ns and 50ns access specifications are limited to a VCC range of 5%. Contact factory for availability.
KEY TIMING PARAMETERS
SPEED -4 -5 -6
tRC tRAC tPC tAA tCAC tCAS tCP
75ns 100ns 110ns
40ns 50ns 60ns
15ns 20ns 25ns
20ns 25ns 30ns
12ns 15ns 15ns
6ns 8ns 10ns
6ns 8ns 10ns
Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE# RAS# NC A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC CASL# CASH# OE# A8 A7 A6 A5 A4 Vss
GENERAL DESCRIPTION
The MT4C16270 is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x16 configuration. The MT4C16270 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins. The MT4C16270 CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and by the last to transition back HIGH. CASL# and CASH# function in a similar manner to CAS# in that either
MT4C16270 W06.pm5 - Rev. 10/96
CASL# or CASH# will generate an internal CAS#. Use of only one of the two results in a BYTE WRITE cycle. CASL# transitioning LOW selects a WRITE cycle for the lower byte (DQ1-DQ8) and CASH# transitioning LOW selects a WRITE cycle for the upper byte (DQ9-DQ16). BYTE READ cycles are achieved through CASL# or CASH# in the same manner.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
FUNCTIONAL BLOCK DIAGRAM
WE# CASL# CASH#
CAS#
CONTROL LOGIC
DATA-IN BUFFER DQ1 16
NO. 2 CLOCK GENERATOR DATA-OUT BUFFER
9
DQ16
9 A0 A1 A2 A3 A4 A5 A6 A7 A8 9
COLUMNADDRESS BUFFER REFRESH CONTROLLER
COLUMN DECODER
16
512
OE#
8
8
SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 9
ROW DECODER
512 x 16
ROWADDRESS BUFFERS (9)
9
512
512 x 512 x 16 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
Vcc Vss
FUNCTIONAL DESCRIPTION
Each bit is uniquely addressed through the 18 address bits during READ or WRITE cycles. These are entered 9 bits (A0 -A8) at a time. RAS# is used to latch the first 9 bits and CAS# the latter 9 bits. The CAS# control also determines whether the cycle will be a refresh cycle (RAS#-ONLY) or an active cycle (READ, WRITE or READ WRITE) once RAS# goes LOW. The MT4C16270 has two CAS# controls, CASL# and CASH#. The CASL# and CASH# inputs internally generate a CAS# signal functioning in a similar manner to the single CAS# input on the other 256K x 16 DRAMs. The key difference is that each CAS# controls its corresponding DQ tristate logic (in conjunction with OE# and WE# and RAS#). CASL# controls DQ1 through DQ8 and CASH# controls DQ9 through DQ16.
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The MT4C16270 CAS# function is determined by the first CAS# (CASL# or CASH# ) transitioning LOW and the last transitioning back HIGH. The two CAS# controls give the MT4C16270 both byte READ and byte WRITE cycle capabilities. (See Figure 2.) A logic HIGH on WE# dictates READ mode while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must
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TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
WORD WRITE RAS# LOWER BYTE WRITE
CASL#
CASH#
WE#
STORED DATA 1 1
INPUT DATA 0 0 1 0 0 0 0 0
INPUT DATA
STORED STORED DATA 0 0 1 0 0 0 0 0 DATA 0 0 1 0 0 0 0 0
INPUT DATA 1 1 0 1 1 1 1 1
INPUT DATA
STORED DATA 1 1 0 1 1 1 1 1
LOWER BYTE (DQ1-DQ8) OF WORD
0 1 1 1 1 1
UPPER BYTE (DQ9-DQ16) OF WORD
0 1 0 1 0 0 0 0
X X X X X X X X
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
X X X X X X X X ADDRESS 1
1 0 1 0 1 1 1 1
ADDRESS 0 X = NOT EFFECTIVE (DON'T CARE)
Figure 1 WORD AND BYTE WRITE EXAMPLE
WORD READ RAS# LOWER BYTE READ
CASL#
CASH#
WE#
LOWER BYTE (DQ1-DQ8) OF WORD
STORED DATA 1 1 0 1 1 1 1 1 0
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED STORED DATA DATA 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
UPPER BYTE (DQ9-DQ16) OF WORD
1 0 1 0 0 0 0
ADDRESS 0 Z = High-Z
ADDRESS 1
Figure 2 WORD AND BYTE READ EXAMPLE
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MT4C16270 256K x 16 DRAM
FUNCTIONAL DESCRIPTION (continued)
be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no write will occur, and the data-outputs will drive read data from the accessed location. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte is not allowed during the same cycle. However, an EARLY WRITE on one byte and, after a CAS# precharge has been satisfied, a LATE WRITE on the other byte is permissable. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O, and pin direction is controlled by OE#, WE# and RAS#. EDO PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A0 -A8) page boundary. The EDO PAGE MODE cycle is always initiated with a row address strobed-in by RAS# followed by a column address strobed-in by CAS#. CAS# may be toggled by holding RAS# LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates the EDO PAGE MODE operation. BYTE ACCESS CYCLE The BYTE WRITE cycle is determined by the use of CASL# and CASH#. Enabling CASL# will select a lower BYTE WRITE cycle (DQ1-DQ8) while enabling CASH# will select an upper BYTE WRITE cycle (DQ9-DQ16). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The MT4C16270 can be viewed as two 256K x 8 DRAMs which have common input controls. Figure 1 illustrates the MT4C16270 BYTE WRITE and WORD WRITE cycles. The BYTE READ is accomplished in the same manner.
RAS#
V IH V IL
CASL#/CASH#
V IH V IL
ADDR
V IH V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH V IOL
OPEN
VALID DATA (A) t OD t OES
VALID DATA (A)
VALID DATA (B) t OD t OEHC
VALID DATA (C) t OD
VALID DATA (D)
OE#
V IH V IL
t OE t OEP
The DQs go back to Low-Z if tOES is met.
The DQs remain High-Z until the next CAS# cycle if tOEHC is met.
The DQs remain High-Z until the next CAS# cycle if tOEP is met. DON'T CARE UNDEFINED
Figure 3 OUTPUT ENABLE AND DISABLE
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MT4C16270 256K x 16 DRAM
EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# goes HIGH, and OE# is LOW (active), the output buffers will be disabled. The MT4C16270 offers an accelerated PAGE MODE cycle by eliminating output disable from CAS# HIGH. This option is called EDO and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and keep OE# HIGH for tOEHC. This will tristate the DQs and they will remain tristate, regardless of OE#, until CAS# falls again. The second method is to have OE# LOW when CAS#
transitions HIGH. Then OE# can pulse HIGH for a minimum of tOEP anytime during the CAS# HIGH period and the DQs will tristate and remain tristate, regardless of OE#, until CAS# falls again (please reference Figure 3 for further detail on the toggling OE# condition). During other cycles, the outputs are disabled at tOFF time after RAS# and CAS# are HIGH, or tWHZ after WE# transitions LOW. The tOFF time is referenced from the rising edge of RAS# or CAS#, whichever occurs last. WE# can also perform the function of turning off the output drivers under certain conditions, as shown in Figure 4. Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is also preconditioned for the next cycle during the RAS# HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR, or HIDDEN) so that all 512 combinations of RAS# addresses (A0-A8) are executed at least every 8ms, regardless of sequence. The CBR REFRESH cycle will also invoke the refresh counter and controller for row address control.
RAS#
V IH V IL
CASL#/CASH#
V IH V IL
ADDR
V IH V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH V IOL
OPEN
VALID DATA (A) t WHZ
VALID DATA (B) t WHZ
INPUT DATA (C)
WE#
V IH V IL V IH V IL
t WPZ
OE#
The DQs go to High-Z if WE# falls, and if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
DON'T CARE UNDEFINED
Figure 4 OUTPUT ENABLE AND DISABLE WITH WE#
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
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MT4C16270 256K x 16 DRAM
TRUTH TABLE
ADDRESSES FUNCTION Standby READ: WORD READ: LOWER BYTE READ: UPPER BYTE WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE: UPPER BYTE (EARLY) READ WRITE EDO-PAGEMODE READ EDO-PAGEEDO1st Cycle 2nd Cycle Any Cycle 1st Cycle 1st Cycle MODE WRITE 2nd Cycle PAGE-MODE 2nd Cycle READ-WRITE HIDDEN REFRESH READ WRITE RAS# H L L L L L L L L L L L L L L LHL LHL L HL CASL# HX L L H L L H L HL HL LH HL HL HL HL L L H L CASH# HX L H L L H L L HL HL LH HL HL HL HL L L H L WE# X H H H L L L HL H H H L L HL HL H L X X OE# X L L L X X X LH L L L X X LH LH L X X X
tR tC
DQs High-Z Data-Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z
NOTES
X ROW ROW ROW ROW ROW ROW ROW ROW n/a n/a ROW n/a ROW n/a ROW ROW ROW X
X COL COL COL COL COL COL COL COL COL n/a COL COL COL COL COL COL n/a X
1, 2 2 2 2 1 1 1, 2 1, 2 2 1, 3 4
RAS#-ONLY REFRESH CBR REFRESH NOTE:
1. These WRITE cycles may also be BYTE WRITE cycles (either CASL# or CASH# active). 2. These READ cycles may also be BYTE READ cycles (either CASL# or CASH# active). 3. EARLY WRITE only. 4. At least one of the two CAS# signals must be active (CASL# or CASH#).
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MT4C16270 256K x 16 DRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin Relative to VSS ..................... -1V to +7V Operating Temperature, TA (ambient) .......... 0C to +70C Storage Temperature (plastic) .................... -55C to +150C Power Dissipation .......................................................... 1.2W Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (VCC = +5V 10%)** PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs INPUT LEAKAGE CURRENT Any input 0V VIN VCC +1.0V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (Q is disabled; 0V VOUT VCC) OUTPUT LEVELS Output High Voltage (IOUT = -2.5mA) Output Low Voltage (IOUT = 2.1mA) SYMBOL VCC** VIH VIL II IOZ VOH VOL MIN 4.5 2.4 -1.0 -2 -10 2.4 0.4 MAX 5.5 VCC+1 0.8 2 10 UNITS V V V A A V V 3 NOTES
PARAMETER/CONDITIONS STANDBY CURRENT: (TTL) (RAS# = CAS# = VIH) STANDBY CURRENT: (CMOS) (RAS# = CAS# = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]; tCP, tASC = 10ns) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS#=VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN])
SYMBOL ICC1 ICC2
-4 2 1
MAX -5 2 1
-6 2 1
UNITS mA mA
NOTES
25
ICC3
205
195
185
mA
4, 40
ICC4
125
120
115
mA
4, 40
ICC5
205
195
185
mA
4
ICC6
180
170
160
mA
4, 5
**40 and 50ns specifications are limited to a VCC range of 5%.
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MT4C16270 256K x 16 DRAM
CAPACITANCE
PARAMETER Input Capacitance: A0-A8 Input Capacitance: RAS#, CASL#, CASH#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 5 7 7 UNITS pF pF pF NOTES 2 2 2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +5V 10%)*
AC CHARACTERISTICS PARAMETER Access time from column-address Column-address setup to CAS# precharge during WRITE Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column-address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR REFRESH) Last CAS# going LOW to first CAS# returning HIGH CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR REFRESH) CAS# to WE# delay time Write command to CAS# lead time Data-in hold time Data-in setup time Output disable time Output Enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay from CAS# or RAS# -4 SYM tAA tACH
tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOEHC tOEP tOES tOFF
-5 MAX 20 MIN 15 40 0 0 48 12 15 8 8 10 10 3 3 8 28 5 40 10 35 8 8 0 3 10 10 10 5 3 5 45 10 40 10 10 0 3 15 10 10 5 3 10,000 10 10 10 10 3 3 10 MAX 25 MIN 15 40 0 0 55
-6 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 15 30 0 0 37 7 6 10 10 3 3 6 25 5 37 10 30 7 7 0 3 6 10 10 5 3
29 21 15, 31 29 37 5, 30 32 31, 41 16, 34 31 30 30 5, 29 21, 29 26, 30 22, 31 22, 31 28, 39, 41 23, 31 27
15 10,000
10,000
35
15 10
15 15
15 15
15
15
15
20, 28, 31, 41
*40ns and 50ns specifications are limited to a VCC range of 5%.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
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MT4C16270 256K x 16 DRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = +5V 10%)*
AC CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time Column-address to RAS# lead time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time Read command hold time (referenced to CAS#) Read command setup time Refresh period (512 cycles) RAS# precharge time RAS# to CAS# precharge time Read command hold time (referenced to RAS#) RAS# hold time READ WRITE cycle time RAS# to WE# delay time Write command to RAS# lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to RAS#) Write command setup time Output disable delay from WE# Write command pulse width WE# pulse widths to disable outputs WE# hold time (CBR REFRESH) WE# setup time (CBR REFRESH) -4 SYM tORD
tPC tPRWC tRAC tRAD tRAH tRAL tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP
-5 MAX MIN 0 20 65 40 50 13 10 17 50 50 100 18 0 0 30 10 0 8 126 69 8 2 8 40 0 3 8 10 10 10 15 10 22 60 60 110 20 0 0 35 10 0 10 140 85 10 2 10 40 0 3 10 10 10 10 MAX MIN 0 25 72
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 0 15 60 7 7 15 40 40 70 17 0 0 25 10 0 7 105 60 7 1 7 30 0 3 7 10 10 10
60
33 33 14 18
10,000 100,000
10,000 100,000
10,000 100,000
17, 29 19, 26, 30 26, 29
8
8
8
19 38 21 26 9, 10 26, 38 26 21, 26, 29 26
50
50
50
13
13
15
*40ns and 50ns specifications are limited to a VCC range of 5%.
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MT4C16270 256K x 16 DRAM
NOTES
1. All voltages referenced to VSS. 2. This parameter is sampled. VCC = 4.75V; f = 1 MHz. 3. NC pins are assumed to be left floating and are not tested for leakage. 4. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the output open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is assured. 7. An initial pause of 100s is required after power-up followed by eight RAS# refresh cycles (RAS#-ONLY or CBR) before proper device operation is assured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 8. AC characteristics assume tT = 2ns. 9. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. If CAS# and RAS# = V IH, data output is High-Z. 12. If CAS# = V IL, data output may contain data from the last valid READ cycle. 13. Measured with a load equivalent to one TTL gate and 50pF, VOL = 0.8V and VOH = 2.0V. 14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 15. Assumes that tRCD tRCD (MAX). 16. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer, CAS# and RAS# must be pulsed HIGH for tCP. 17. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC [tRAC (MIN) no longer applied]. With or without the tRCD (MAX) limit, tAA (MIN), tRAC (MIN) and tCAC (MIN) must always be met. 18. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA [tRAC (MIN) and tCAC (MIN) no longer applied]. With or without the tRAD (MAX) limit, tAA (MIN), tRAC (MIN) and tCAC (MIN) must always be met. 19. Either tRCH or tRRH must be satisfied for a READ cycle. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 21. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of Q (at access time and until CAS# and RAS# or OE# go back to V IH) is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#controlled) cycle. 22. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. During a READ cycle, if OE# is LOW then taken HIGH before CAS# goes HIGH, Q goes open. If OE# is tied permanently LOW, a LATE WRITE or READMODIFY-WRITE operation is not possible. 24. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 25. All other inputs at VCC -0.2V. 26. Write command is defined as WE# going LOW. 27. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously written data if CAS# remains LOW and OE# is taken back LOW after tOEH is met.
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MT4C16270 256K x 16 DRAM
NOTES (continued)
28. The DQs open during READ cycles once tOD or tOFF occur. 29. The first CAS#x edge to transition LOW. 30. The last CAS#x edge to transition HIGH. 31. Output parameter (DQx) is referenced to corresponding CAS# input, DQ1-DQ8 by CASL# and DQ9-DQ16 by CASH#. 32. Last falling CAS#x edge to first rising CAS#x edge. 33. Last rising CAS#x edge to next cycle's last rising CAS#x edge. 34. Last rising CAS#x edge to first falling CAS#x edge. 35. First DQs controlled by the first CAS#x to go LOW. 36. Last DQs controlled by the last CAS#x to go HIGH. 37. Each CAS#x must meet minimum pulse width. 38. Last CAS#x to go LOW. 39. All DQs controlled, regardless CASL# and CASH#. 40. Column address changed once each cycle. 41. The 3ns minimum is a parameter guaranteed by design.
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MT4C16270 256K x 16 DRAM
READ CYCLE
tRC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCRP tRCD tCAS tCLCH tRRH
CASH#/CASL#
V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tRAL tCAH
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL NOTE 1 tOFF
OPEN t OE
VALID DATA t OD
OPEN
OE#
V IH V IL t OES
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA
tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD tOE tOES
-5 MAX 20 MIN 40 0 0 12 15 8 10,000 8 10 3 5 15 10 5 40 3 15 15 5 10,000 10 10 10 3 5 40 3 MAX 25 MIN 40 0 0
-6 MAX 30 UNITS ns ns ns 15 10,000 ns ns ns ns ns ns ns 15 15 5 ns ns ns ns SYM tOFF
tRAC tRAD tRAH tRAL tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-4 MIN 3 7 7 15 40 75 17 0 0 25 0 8 MAX 15 40 13 10 17 50 100 18 0 0 30 0 10 MIN 3
-5 MAX 15 50 15 10 22 60 110 20 0 0 35 0 15 MIN 3
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 30 0 0 7 6 10 3 5 37 3
10,000
10,000
10,000
NOTE: 1. tOFF is referenced from the rising edge of RAS# or CAS#, whichever occurs last.
MT4C16270 W06.pm5 - Rev. 10/96 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
12
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
EARLY WRITE CYCLE
tRC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCRP tRCD tCAS tCLCH
CASL#/CASH#
V IH V IL tAR tRAD tASR tRAH tASC tRAL tCAH tACH V IH V IL
ADDR
ROW
COLUMN tCWL tRWL tWCR tWCS tWCH tWP
ROW
WE#
V IH V IL tDS tDH
V DQ V IOH IOL V IH V IL
VALID DATA
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tACH
tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS tRAD
-5 MAX MIN 15 40 0 0 10,000 8 8 10 5 40 8 8 0 13 10,000 MAX MIN 15 40 0 0 10 10 10 5 40 10 10 0 15
-6 MAX UNITS ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns SYM tRAH
tRAL tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-4 MIN 7 15 40 75 17 25 7 7 7 30 0 7 MAX MIN 10 17 50 100 18 30 8 8 8 40 0 8
-5 MAX MIN 10 22 60 110 20 35 10 10 10 40 0 10
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 15 30 0 0 7 6 10 5 37 7 7 0 7
10,000
10,000
10,000
MT4C16270 W06.pm5 - Rev. 10/96
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCRP tRCD tCAS tCLCH
CASL#/CASH#
V IH V IL tAR tRAD tASR tRAH tASC tRAL tCAH tACH
ADDR
V IH V IL
ROW
COLUMN tRWD tRCS tCWD tAWD tCWL tRWL tWP
ROW
WE#
V IH V IL tAA tRAC tCAC t CLZ tDS tDH
V DQ V IOH IOL
OPEN tOE
VALID D OUT tOD
VALID D IN tOEH
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA
tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL tDH tDS
-5 MAX 30 MIN 15 40 0 0 48 12 15 8 10,000 8 10 3 5 40 35 8 8 0 10,000 10 10 10 3 5 40 40 10 10 0 MAX 25 MIN 15 40 0 0 55
-6 MAX 30 UNITS ns ns ns ns ns ns 15 10,000 ns ns ns ns ns ns ns ns ns ns ns SYM tOD
tOE tOEH tRAC tRAD tRAH tRAL tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-4 MIN 3 6 40 7 7 15 40 17 0 25 7 105 60 7 7 10,000 13 10 17 50 18 0 30 8 126 69 8 8 MAX 15 10 10 MIN 3
-5 MAX 15 15 15 50 15 10 10,000 22 60 20 0 35 10 140 85 10 10 MIN 3
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 15 30 0 0 37 7 6 10 3 5 37 30 7 7 0
10,000
MT4C16270 W06.pm5 - Rev. 10/96
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
EDO-PAGE-MODE READ CYCLE
tRASP tRP
RAS#
V IH V IL tCSH tCRP tRCD tCAS, tCLCH tPC tCP (NOTE 1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CASH#/CASL#
V IH V IL tAR tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL
ADDR
V IH V IL
ROW
COLUMN
COLUMN
COLUMN
ROW tRRH
tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL OPEN tOE V IH V IL tOES tCOH VALID DATA VALID DATA tOD tAA tCPA tCAC tCLZ tAA tCPA tCAC
tRCH
tOFF VALID DATA tOE tOES tOD OPEN
tOEHC
OE#
tOEP
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA tAR
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE
-5 MAX 20 MIN 40 0 0 12 15 8 8 10 3 3 8 25 28 5 40 15 10 3 15 15 5 40 3 10,000 10 10 10 3 3 10 MAX 25 MIN 40 0 0
-6 MAX 30 UNITS ns ns ns ns 15 10,000 ns ns ns ns ns ns ns ns ns ns 15 15 ns ns SYM tOEHC tOEP
tOES tOFF tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRRH tRSH
-4 MIN 10 10 5 3 15 40 7 7 15 40 17 0 0 25 0 7 100,000 13 10 17 50 18 0 0 30 0 8 MAX MIN 10 10 5 3 20
-5 MAX MIN 10 10 5 3 25 50 15 10 22 100,000 60 20 0 0 35 0 10
-6 MAX UNITS ns ns ns ns ns ns ns ns ns 100,000 ns ns ns ns ns ns ns
MIN 30 0 0 7 6 10 3 3 6 5 37 3
15
15
15 60
10,000
35
NOTE: 1. tPC can be measured from falling edge of CAS# to falling edge of CAS#, or from rising edge of CAS# to rising edge of CAS#. Both measurements must meet the tPC specification.
MT4C16270 W06.pm5 - Rev. 10/96
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP tRP
RAS#
V IH V IL tCSH tCRP tRCD tCAS, tCLCH tPC tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CASL#/CASH#
V IH V IL tAR tRAD tASR tRAH tASC tACH tCAH tASC tACH tCAH tASC tACH tRAL tCAH
ADDR
V IH V IL
ROW
COLUMN tCWL tWCS tWCH tWP
COLUMN tCWL tWCS tWCH tWP
COLUMN tCWL tWCS tWCH tWP
ROW
WE#
V IH V IL tWCR tDS tDH tDS tDH tDS tRWL tDH
V DQ V IOH IOL
VALID DATA
VALID DATA
VALID DATA
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM
tACH tAR tASC tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS
-5 MAX MIN 15 40 0 0 8 8 10 8 5 40 8 8 0 MAX MIN 15 40 0 0 10 10 10 10 5 40 10 10 0
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYM
tPC tRAD tRAH tRAL tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-4 MIN 15 7 7 15 40 17 25 7 7 7 30 0 7 100,000 MAX MIN 20 13 10 17 50 18 30 8 8 8 40 0 8
-5 MAX MIN 25 15 10 100,000 22 60 20 35 10 10 10 40 0 10
-6 MAX UNITS ns ns ns 100,000 ns ns ns ns ns ns ns ns ns ns
MIN 15 30 0 0 7 6 10 6 5 37 7 7 0
10,000
10,000
10,000
MT4C16270 W06.pm5 - Rev. 10/96
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP tRP
RAS#
V IH V IL tCSH tCRP tRCD tCAS, tCLCH tCP t PC tPRWC NOTE 1 tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CAS#L/CASH#
V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tRAL
ADDR
ROW
COLUMN tRWD tRCS tCWL tWP tAWD tCWD
COLUMN
COLUMN tRWL tCWL
ROW
tWP tAWD tCWD
tAWD tCWD
tCWL tWP
WE#
V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID D OUT VALID D IN tOD tOE tOE VALID D OUT VALID D IN tOD tOE tDH tDS tAA tCPA tCAC tCLZ VALID D OUT VALID D IN tOD OPEN tDH tDS
DQ
V IOH V IOL
OPEN
t OEH
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA tAR
tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS
-5 MAX 20 MIN 40 0 0 48 12 15 8 10,000 8 10 3 8 25 28 5 40 35 8 8 0 5 40 40 10 10 0 10,000 10 10 10 3 10 MAX 25 MIN 40 0 0 55
-6 MAX 30 UNITS ns ns ns ns 15 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOD tOE
tOEH tPC tPRWC tRAC tRAD tRAH tRAL tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-4 MIN 3 6 15 60 40 7 7 15 40 17 0 25 7 60 7 7 100,000 13 10 17 50 18 0 30 8 69 8 8 MAX 15 10 MIN 3 10 20 65
-5 MAX 15 15 MIN 3 15 25 72 50 15 10 22 100,000 60 20 0 35 10 85 10 10
-6 MAX 15 15 UNITS ns ns ns ns 60 ns ns ns ns ns 100,000 ns ns ns ns ns ns ns ns
MIN 30 0 0 37 7 6 10 3 6 5 37 30 7 7 0
35
NOTE: 1. tPC can be measured from falling edge to falling edge of CAS#, or from rising edge to rising edge of CAS#. Both measurements must meet the tPC specification.
MT4C16270 W06.pm5 - Rev. 10/96
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
t RASP t RP
RAS#
V IH V IL t CSH t PC t CRP V IH V IL t ACH t AR t RAD tASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH t RAL t RCD t CAS t CP t CAS t PC t CP t RSH t CAS t CP
CASL#/CASH#
ADDR
V IH V IL
ROW
COLUMN (A) t RCS
COLUMN (B) t RCH t WCS
COLUMN (N) t WCH
ROW
WE#
V IH V IL t RAC
t AA t CPA t CAC
t AA t WHZ t CAC t COH t DS t DH
DQ V IOH V IOL V IH V IL
OPEN t OE
VALID DATA (A)
VALID DATA (B)
VALID DATA IN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA
tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS
-5 MAX 20 MIN 15 40 0 0 12 15 8 8 3 8 25 28 5 40 8 0 5 40 10 0 10,000 10 10 3 10 MAX 25 MIN 15 40 0 0
-6 MAX 30 UNITS ns ns ns ns 15 10,000 ns ns ns ns ns ns ns ns ns ns ns SYM tOE
tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ
-4 MIN 15 40 7 7 15 40 17 0 0 25 7 7 0 3 13 100,000 13 10 17 50 18 0 0 30 8 8 0 3 MAX 10 MIN 20
-5 MAX 15 50 15 10 22 100,000 60 20 0 0 35 10 10 13 0 3 MIN 25
-6 MAX 15 60 UNITS ns ns ns ns ns ns 100,000 ns ns ns ns ns ns ns 15 ns ns
MIN 15 37 0 0 7 6 3 6 5 37 7 0
10,000
35
MT4C16270 W06.pm5 - Rev. 10/96
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
READ CYCLE (with WE#-controlled disable)
RAS#
V IH V IL tCSH tCRP tRCD tCAS tCP
CASL#/CASH#
V IH V IL tAR tRAD tASR V IH V IL tWRP tRAH tASC tCAH tASC
ADDR
ROW tWRH tRCS
COLUMN tRCH tWPZ tRCS
COLUMN
WE#
V IH V IL
NOTE 1
tAA tRAC tCAC tCLZ tWHZ tCLZ
DQ
V OH V OL
OPEN t OE
VALID DATA t OD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA tAR
tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tOD
-5 MAX 20 MIN 40 0 0 12 15 8 8 3 8 5 40 15 3 15 10,000 10 10 3 10 5 40 3 MAX 25 MIN 40 0 0
-6 MAX 30 UNITS ns ns ns ns 15 10,000 ns ns ns ns ns ns ns 15 ns SYM tOE
tRAC tRAD tRAH tRCH tRCD tRCS tWHZ tWPZ tWRH tWRP
-4 MIN MAX 10 40 7 7 0 17 0 3 10 10 10 13 13 10 0 18 0 3 10 10 10 MIN
-5 MAX 15 50 15 10 0 20 13 0 3 10 10 10 MIN
-6 MAX 15 60 UNITS ns ns ns ns ns ns 15 ns ns ns ns ns
MIN 30 0 0 7 6 3 6 5 37 3
10,000
NOTE: 1. Although WE# is a "don't care" at RAS# time during an access cycle (READ or WRITE), the system designer should implement WE# HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
MT4C16270 W06.pm5 - Rev. 10/96
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
RAS#-ONLY REFRESH CYCLE (OE#, WE# = DON'T CARE)
tRC tRAS tRP
RAS#
V IH V IL tCRP V IH V IL tASR V IH V IL tRAH tRPC
CASL#/CASH#
ADDR
ROW
ROW
V Q V OH OL
OPEN tWRP tWRH NOTE 1 tWRP tWRH
WE#
V IH V IL
CBR REFRESH CYCLE (Addresses; OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CASH#, CASL# V IH V IL V OH V OL V IH V IL OPEN tCSR tCHR tRPC tCSR tCHR tRAS tRP tRAS
DQ WE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tASR tCHR
tCP tCRP tCSR tRAH
-5 MAX MIN 0 10 8 5 10 10 MAX MIN 0 10 10 5 10 10
-6 MAX UNITS ns ns ns ns ns ns SYM tRAS
tRC tRP tRPC tWRH tWRP
-4 MIN 40 75 25 10 10 10 MAX 10,000 MIN 50 100 30 10 10 10
-5 MAX 10,000 MIN 60 110 35 10 10 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 10 6 5 10 7
NOTE: 1. Although WE# is a "don't care" at RAS# time during an access cycle (READ or WRITE), the system designer should implement WE# HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
MT4C16270 W06.pm5 - Rev. 10/96
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
HIDDEN REFRESH CYCLE 24 (WE# = HIGH; OE# = LOW)
tRAS tRP tRAS
RAS#
V IH V IL tCRP tRCD tRSH tCHR
CASL#/CASH#
V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tRAL tCAH
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ NOTE 1 tOFF
DQx
V OH V OL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
tORD
DON'T CARE UNDEFINED
TIMING PARAMETERS
-4 SYM tAA
tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD tOE
-5 MAX 20 MIN 40 0 0 12 15 8 10 3 5 3 10 10 3 5 3 MAX 25 MIN 40 0 0
-6 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYM tOFF
tORD tRAC tRAD tRAH tRAL tRAS tRCD tRP tRSH
-4 MIN 3 0 40 7 7 15 40 17 25 7 10,000 13 10 17 50 18 30 8 MAX 15 MIN 3 0
-5 MAX 15 50 15 10 10,000 22 60 20 35 10 MIN 3 0
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns
MIN 30 0 0 7 10 3 5 3
15
10,000
15 10
15 15
15 15
NOTE: 1. tOFF is referenced from the rising edge of RAS# or CAS#, whichever occurs last.
MT4C16270 W06.pm5 - Rev. 10/96
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.
TECHNOLOGY, INC.
MT4C16270 256K x 16 DRAM
40-PIN PLASTIC SOJ (400 mil) DA-6
1.029 (26.14) 1.023 (25.98)
.405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP .950 (24.13)
.032 (0.81) .026 (0.66)
.150 (3.81) .138 (3.51)
.105 (2.67) .090 (2.29)
SEATING PLANE
.037 (0.94) MAX DAMBAR PROTRUSION
.020 (0.51) .015 (0.38)
.380 (9.65) .360 (9.14)
.025 (0.64) MIN
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
MT4C16270 W06.pm5 - Rev. 10/96
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1996, Micron Technology, Inc.

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